Hector Pettenghi

Publicações

Artigos completos publicados em periódicos

1.PETTENGHI, H.; CHAVES, R. ; MATOS, R.; SOUSA, L. Method for designing two levels RNS reverse converters for large dynamic ranges. Integration (Amsterdam. Print)

, v. 55, p. 22-29, 2016.

2.PETTENGHI, H.; PRATAS, F. ; SOUSA, L. . Method for Designing Efficient Mixed Radix Multipliers. Circuits, Systems, and Signal Processing

, v. 1, p. 1, 2014.

Citações:

14 |

3. PETTENGHI, H.; SOUSA, L. . Method to Design General RNS Reverse Converters for Extended Moduli Sets. IEEE Transactions on Circuits and Systems II: Express Briefs, v. 60, p. 877-881, 2013.

Citações:

4 |

4. PETTENGHI, H; CHAVES, RICARDO ; SOUSA, LEONEL . RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to $(8n+1)$ -bit. IEEE Transactions on Circuits and Systems. I, Regular Papers (Online), v. 60, p. 1487-1500, 2013.

Citações:

16 |

5.PETTENGHI, H.; JAYASINGHE, DARSHANA ; AMBROSE, JUDE ANGELO ; SOUSA, LEONEL . Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks. IET Circuits, Devices & Systems (Print)

, v. 7, p. 283-293, 2013.

Citações:

2 |

6.PETTENGHI, H.; COTOFANA, SORIN ; SOUSA, LEONEL . EFFICIENT METHOD FOR DESIGNING MODULO {2 ± k} MULTIPLIERS. Journal of Circuits, Systems, and Computers

, v. 23, p. 1450001, 2013.

Citações:

2 |

7. PETTENGHI, H.; AVEDILLO, MARÍA J. ; QUINTANA, JOSÉ M. . Improved Nanopipelined RTD Adder Using Generalized Threshold Gates. IEEE Transactions on Nanotechnology, v. 10, p. 155-162, 2011.

Citações:

4 |

8.QUINTANA, J.M. ; AVEDILLO, M.J. ; NUNEZ, J. ;PETTENGHI, H. Operation Limits for RTD-Based MOBILE Circuits. IEEE Transactions on Circuits and Systems. I, Regular Papers (Print)

, v. 56, p. 350-363, 2009.

Citações:

4 |

9. PETTENGHI, H.; AVEDILLO, MARÍA J. ; QUINTANA, JOSÉ M. . Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectronics (Luton) (Cessou em 1978. Cont. ISSN 0959-8324 Microelectronics Journal)

, v. 39, p. 241-247, 2008.

Citações:

11 |

10.AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. . Increased Logic Functionality of Clocked Series-Connected RTDS. IEEE Transactions on Nanotechnology

, v. 5, p. 606-611, 2006.

Citações:

12 |

11.AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. . Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Transactions on Circuits and Systems. II, Analog and Digital Signal Processing (Cessou em 2002. Funfiu-se com ISSN 1057-7122 e 1549-8328)

, v. 53, p. 334-338, 2006.

Citações:

12 |

12.PETTENGHI, H.; AVEDILLO, M.J. ; QUINTANA, J.M. . Single phase clock scheme for mobile logic gates. Electronics Letters

, v. 42, p. 1382, 2006.

Citações:

7 |

13.AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. ; KELLY, P.M. ; THOMPSON, C.J. . Multi-threshold threshold logic circuit design using resonant tunnelling devices. Electronics Letters

, v. 39, p. 1502, 2003.

Citações:

31 |

Trabalhos completos publicados em anais de congressos

1.PETTENGHI, H.; R. De Matos ; PALUDO, R. ; P. Lyakhov . Efficient Implementation of Modular Multiplication by Constants Applied to RNS Reverse Converters. In: 2017 IEEE International Symposium on Circuits & Systems, 2017, Baltimore. Efficient Implementation of Modular Multiplication by Constants Applied to RNS Reverse Converters, 2017.

2.PETTENGHI, HECTOR; DE MATOS, ROBERTO ; MOLAHOSSEINI, AMIR . RNS reverse converters for moduli sets with dynamic ranges of 9n-bit. In: 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016, Florianopolis. 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016. p. 143.

3.PETTENGHI, H.; SOUSA, LEONEL . RNS Reverse Converters based on the New Chinese Remainder Theorem I. In: International Symposium on Circuits and Systems (ISCAS15), 2015, Lisboa, Portugal. Proceedings of Int. Symp. on Circuits and Syst. (ISCAS15), 2015.

4.PETTENGHI, H.; SOUSA, LEONEL ; AMBROSE, JUDE ANGELO . Novel methodology to improve Multi-moduli architectures for Binary-to-RNS conversion. In: XXX Conference on Design of Circuits and Integrated Systems, 2015, Estoril. Conference on Design of Circuits and Integrated Systems, 2015.

5.PETTENGHI, H.; CHAVES, RICARDO ; SOUSA, LEONEL . Method for designing Multi-Channel RNS Architectures to prevent Power Analysis SCA. In: Int. Symp. on Circuits and Syst. (ISCAS14), 2014, Melbourne. Proceedings of Int. Symp. on Circuits and Syst. (ISCAS14), 2014.

6.AMBROSE, JUDE ANGELO ; PETTENGHI, HECTOR ; SOUSA, LEONEL . DARNS:A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. In: 2013 18th Asia and South Pacific Design Automation Conference (ASPDAC), 2013, Yokohama. 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013. p. 620.

7.PETTENGHI, H.; CHAVES, RICARDO ; SOUSA, LEONEL . Method for designing modulo {2^n±k} Binary-to-RNS converters. In: Conference on Design of Circuits and Integrated Systems (2013), 2013, San Sebastian (Spain). Proceedings of Conference on Design of Circuits and Integrated Systems, 2013.

8.MATUTINO, PEDRO MIGUENS ; PETTENGHI, HECTOR ; CHAVES, RICARDO ; SOUSA, LEONEL . RNS Arithmetic Units for Modulo {2^n+-k}. In: 2012 15th Euromicro Conference on Digital System Design (DSD), 2012, Cesme. 2012 15th Euromicro Conference on Digital System Design, 2012. p. 795.

9.PETTENGHI, HECTOR; SOUSA, LEONEL ; AMBROSE, JUDE ANGELO . Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. In: 2012 17th Asia and South Pacific Design Automation Conference (ASPDAC), 2012, Sydney. 17th Asia and South Pacific Design Automation Conference, 2012. p. 819.

10.MATUTINO, P. M. ; PETTENGHI, HECTOR ; CHAVES, RICARDO ; SOUSA, LEONEL . Multiplier-based binary-to-RNS converter modulo {2n±k}. In: Conference on Design of Circuits and Integrated Systems (DCIS), 2011, Albufeira (Portugal). Multiplier-based binary-to-RNS converter modulo {2n±k}, 2011.

11.PETTENGHI, HECTOR; CHAVES, RICARDO ; SOUSA, LEONEL ; AVEDILLO, MARIA J. . An improved RNS generator 2n ± k based on threshold logic. In: 2010 18th IEEE/IFIP International Conference on VLSI and SystemonChip (VLSISoC), 2010, Madrid. 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010. p. 119.

12.PETTENGHI, HECTOR; AVEDILLO, MARIA J. ; QUINTANA, JOSE M. . A novel contribution to the RTD-based threshold logic family. In: 2008 IEEE International Symposium on Circuits and Systems ISCAS 2008, 2008, Seattle. 2008 IEEE International Symposium on Circuits and Systems, 2008. p. 2350.

13.PETTENGHI, HÉCTOR; AVEDILLO, MARIA J. ; QUINTANA, J.M. . RTD based Logic Circuits Using Generalized Threshold Gates. In: Conference on Design of Circuits and Integrated Systems (2008), 2008, Grenoble (France). Proceedings of Conference on Design of Circuits and Integrated Systems, 2008.

14.PETTENGHI, HECTOR; AVEDILLO, MARIA J. ; QUINTANA, JOSE M. . Non Return Mobile Logic Family. In: 2007 IEEE International Symposium on Circuits and Systems, 2007, New Orleans. 2007 IEEE International Symposium on Circuits and Systems, 2007. p. 125.

15.ROLDAN, H.P.; AVEDILLO, MARIA J. ; QUINTANA, J.M. . Single Phase Clock Scheme for Mobile Based Circuits. In: Conference on Design of Circuits and Integrated Systems (2006), 2006, Barcelona (Spain). Conference on Design of Circuits and Integrated Systems, 2006.

16.QUINTANA, J.M. ; AVEDILLO, MARIA J. ; PETTENGHI, H. . Implementación de lógica umbral y multiumbral con RTDs. In: IBERCHIP, 2006, San José. IBERCHIP, 2006.

17.QUINTANA, J.M. ; AVEDILLO, M.J. ; PETTENGHI, H. . Self-latching operation limits for MOBILE circuits. In: 2006 IEEE International Symposium on Circuits and Systems, 2006, Island of Kos. 2006 IEEE International Symposium on Circuits and Systems. p. 4.

18.PETTENGHI, H.; AVEDILLO, MARÍA J. ; QUINTANA, J.M. . Using Multi-Threshold Threshold Gates in RTDbased Logic Design. A Case Study. In: European Nano Systems 2005 (ENS), 2005, Paris. Proceedings of the European Nano Systems 2005 (ENS), 2005.

19.ROLDAN, H.P.; AVEDILLO, MARIA J. ; QUINTANA, J.M. . Nanopipelined RTD adders using Multi-Threshold Threshold Gates. In: Conference on Design of Circuits and Integrated Systems (2005), 2005, Lisbon (Portugal). Proceedings of Conference on Design of Circuits and Integrated Systems, 2005.

20.QUINTANA, J.M. ; AVEDILLO, MARÍA J. ; PETTENGHI, HECTOR . Design of Residue Generators using Threshold Logic. In: International Symposium on Micro-NanoMechatronics and Human Science, 2005, Nagoya. International Symposium on Micro-NanoMechatronics and Human Science, 2005. v. 3.

21.AVEDILLO, M.J. ; QUINTANA, J.M. ; PETTENGHI, H. . Logic Models Supporting the Design of MOBILE-based RTD Circuits. In: 2005 IEEE International Conference on ApplicationSpecific Systems, Architecture Processors (ASAP’05), 2005, Samos. 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP’05). p. 254.

22.QUINTANA, J.M. ; AVEDILLO, M.J. ; PETTENGHI, H. . Programmable logic gate based on resonant tunnelling devices. In: 2004 IEEE International Symposium on Circuits and Systems, 2004, Vancouver. 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512). p. III.

23.QUINTANA, J.M. ; AVEDILLO, M.J. ; PETTENGHI, H. . RTD-based compact programmable gates. In: 2004 IEEE International Joint Conference on Neural Networks, 2004, Budapest. 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541). p. 2637.

24.PETTENGHI, H.; AVEDILLO, MARIA J. ; QUINTANA, J.M. . A CAD tool for the design of RTD programmable gates based on MOBILE. In: Conference on Design of Circuits and Integrated Systems (2004), 2004, Burdeos. Proceedings of Conference on Design of Circuits and Integrated Systems, 2004.

25.PETTENGHI, H.; AVEDILLO, M.J. ; QUINTANA, J.M. . Useful logic blocks based on clocked series-connected RTDs. In: 4th IEEE Conference on Nanotechnology, 2004., 2004, Munich. 4th IEEE Conference on Nanotechnology, 2004.. p. 593.

26.QUINTANA, J.M. ; AVEDILLO, MARIA J. ; PETTENGHI, H. . Design of Residue Generators Modulo-3 by using Threshold Logic. In: Conference on Design of Circuits and Integrated Systems, 2003, Ciudad Real (Spain). Proceedings of Conference on Design of Circuits and Integrated Systems, 2003.

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